315 lines
8.5 KiB
C
Executable File
315 lines
8.5 KiB
C
Executable File
/**
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* \file at86rf233.h
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*
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* \brief AT86RF233 registers description and interface
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*
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* Copyright (C) 2012-2014, Atmel Corporation. All rights reserved.
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*
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* \asf_license_start
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. The name of Atmel may not be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* 4. This software may only be redistributed and used in connection with an
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* Atmel microcontroller product.
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*
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* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* \asf_license_stop
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*
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* Modification and other use of this code is subject to Atmel's Limited
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* License Agreement (license.txt).
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*
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* $Id: at86rf233.h 9267 2014-03-18 21:46:19Z ataradov $
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*
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*/
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#ifndef _AT86RF233_H_
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#define _AT86RF233_H_
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/*- Definitions ------------------------------------------------------------*/
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#define AES_BLOCK_SIZE 16
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#define AES_CORE_CYCLE_TIME 24 // us
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#define RANDOM_NUMBER_UPDATE_INTERVAL 1 // us
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/*- Types ------------------------------------------------------------------*/
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#define TRX_STATUS_REG 0x01
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#define TRX_STATE_REG 0x02
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#define TRX_CTRL_0_REG 0x03
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#define TRX_CTRL_1_REG 0x04
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#define PHY_TX_PWR_REG 0x05
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#define PHY_RSSI_REG 0x06
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#define PHY_ED_LEVEL_REG 0x07
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#define PHY_CC_CCA_REG 0x08
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#define CCA_THRES_REG 0x09
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#define RX_CTRL_REG 0x0a
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#define SFD_VALUE_REG 0x0b
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#define TRX_CTRL_2_REG 0x0c
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#define ANT_DIV_REG 0x0d
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#define IRQ_MASK_REG 0x0e
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#define IRQ_STATUS_REG 0x0f
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#define VREG_CTRL_REG 0x10
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#define BATMON_REG 0x11
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#define XOSC_CTRL_REG 0x12
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#define RX_SYN_REG 0x15
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#define TRX_RPC_REG 0x16
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#define XAH_CTRL_1_REG 0x17
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#define FTN_CTRL_REG 0x18
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#define XAH_CTRL_2_REG 0x19
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#define PLL_CF_REG 0x1a
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#define PLL_DCU_REG 0x1b
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#define PART_NUM_REG 0x1c
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#define VERSION_NUM_REG 0x1d
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#define MAN_ID_0_REG 0x1e
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#define MAN_ID_1_REG 0x1f
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#define SHORT_ADDR_0_REG 0x20
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#define SHORT_ADDR_1_REG 0x21
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#define PAN_ID_0_REG 0x22
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#define PAN_ID_1_REG 0x23
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#define IEEE_ADDR_0_REG 0x24
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#define IEEE_ADDR_1_REG 0x25
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#define IEEE_ADDR_2_REG 0x26
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#define IEEE_ADDR_3_REG 0x27
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#define IEEE_ADDR_4_REG 0x28
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#define IEEE_ADDR_5_REG 0x29
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#define IEEE_ADDR_6_REG 0x2a
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#define IEEE_ADDR_7_REG 0x2b
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#define XAH_CTRL_0_REG 0x2c
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#define CSMA_SEED_0_REG 0x2d
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#define CSMA_SEED_1_REG 0x2e
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#define CSMA_BE_REG 0x2f
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#define TST_CTRL_DIGI_REG 0x36
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#define PHY_TX_TIME_REG 0x3b
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#define PHY_PMU_VALUE_REG 0x3b
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#define TST_AGC_REG 0x3c
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#define TST_SDM_REG 0x3d
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#define AES_STATUS_REG 0x82
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#define AES_CTRL_REG 0x83
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#define AES_KEY_REG 0x84
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#define AES_STATE_REG 0x84
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#define AES_CTRL_M_REG 0x94
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// TRX_STATUS
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#define CCA_DONE 7
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#define CCA_STATUS 6
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#define TRX_STATUS 0
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// TRX_STATE
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#define TRAC_STATUS 5
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#define TRX_CMD 0
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// TRX_CTRL_0
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#define TOM_EN 7
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#define PMU_EN 4
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#define PMU_IF_INVERSE 4
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#define CLKM_SHA_SEL 3
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#define CLKM_CTRL 0
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// TRX_CTRL_1
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#define PA_EXT_EN 7
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#define IRQ_2_EXT_EN 6
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#define TX_AUTO_CRC_ON 5
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#define RX_BL_CTRL 4
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#define SPI_CMD_MODE 2
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#define IRQ_MASK_MODE 1
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#define IRQ_POLARITY 0
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// PHY_TX_PWR
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#define TX_PWR 0
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// PHY_RSSI
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#define RX_CRC_VALID 7
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#define RND_VALUE 5
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#define RSSI 0
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// PHY_CC_CCA
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#define CCA_REQUEST 7
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#define CCA_MODE 5
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#define CHANNEL 0
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// CCA_THRES
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#define CCA_ED_THRES 0
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// RX_CTRL_REG
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#define PEL_SHIFT_VALUE 6
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#define PDT_THRES 0
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// TRX_CTRL_2
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#define RX_SAFE_MODE 7
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#define OQPSK_SCRAM_EN 5
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#define OQPSK_DATA_RATE 0
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// ANT_DIV
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#define ANT_SEL 7
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#define ANT_DIV_EN 3
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#define ANT_EXT_SW_EN 2
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#define ANT_CTRL 0
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// IRQ_MASK, IRQ_STATUS
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#define BAT_LOW 7
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#define TRX_UR 6
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#define AMI 5
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#define CCA_ED_DONE 4
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#define TRX_END 3
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#define RX_START 2
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#define PLL_UNLOCK 1
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#define PLL_LOCK 0
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// VREG_CTRL
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#define AVREG_EXT 7
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#define AVDD_OK 6
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#define DVREG_EXT 3
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#define DVDD_OK 2
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// BATMON
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#define BATMON_OK 5
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#define BATMON_HR 4
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#define BATMON_VTH 0
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// XOSC_CTRL
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#define XTAL_MODE 4
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#define XTAL_TRIM 0
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// RX_SYN
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#define RX_PDT_DIS 7
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#define RX_PDT_LEVEL 0
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// TRX_RPC
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#define RX_RPC_CTRL 6
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#define RX_RPC_EN 5
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#define PDT_RPC_EN 4
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#define PLL_RPC_EN 3
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#define XAH_TX_RPC_EN 2
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#define IPAN_RPC_EN 1
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// XAH_CTRL_1
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#define ARET_TX_TS_EN 7
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#define AACK_FLTR_RES_FT 5
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#define AACK_UPLD_RES_FT 4
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#define AACK_ACK_TIME 2
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#define AACK_PROM_MODE 1
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#define AACK_SPC_EN 0
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// FTN_CTRL
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#define FTN_START 7
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#define FTNV 0
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// XAH_CTRL_2
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#define ARET_FRAME_RETRIES 4
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#define ARET_CSMA_RETRIES 1
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// PLL_CF
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#define PLL_CF_START 7
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#define PLL_CF 0
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// PLL_DCU
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#define PLL_DCU_START 7
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// XAH_CTRL_0
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#define MAX_FRAME_RETRES 4
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#define MAX_CSMA_RETRES 1
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#define SLOTTED_OPERATION 0
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// CSMA_SEED_1
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#define AACK_FVN_MODE 6
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#define AACK_SET_PD 5
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#define AACK_DIS_ACK 4
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#define AACK_I_AM_COORD 3
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#define CSMA_SEED_1 0
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// CSMA_BE
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#define MAX_BE 4
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#define MIN_BE 0
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// TST_CTRL_DIGI
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#define TST_CTRL_DIG 0
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// PHY_TX_TIME_REG
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#define IRC_TX_TIME 0
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// TST_AGC_REG
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#define AGC_HOLD_SEL 5
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#define AGC_RST 4
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#define AGC_OFF 3
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#define AGC_HOLD 2
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#define GC 0
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// TST_SDM_REG
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#define MOD_SEL 7
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#define MOD 6
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#define TX_RX 5
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#define TX_RX_SEL 4
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// AES_CTRL
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#define AES_CTRL_DIR 3
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#define AES_CTRL_MODE 4
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#define AES_CTRL_REQUEST 7
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// AES_STATUS
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#define AES_STATUS_DONE 0
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#define AES_STATUS_ER 7
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#define RF_CMD_REG_W ((1<<7) | (1<<6))
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#define RF_CMD_REG_R ((1<<7) | (0<<6))
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#define RF_CMD_FRAME_W ((0<<7) | (1<<6) | (1<<5))
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#define RF_CMD_FRAME_R ((0<<7) | (0<<6) | (1<<5))
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#define RF_CMD_SRAM_W ((0<<7) | (1<<6) | (0<<5))
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#define RF_CMD_SRAM_R ((0<<7) | (0<<6) | (0<<5))
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#define TRX_CMD_NOP 0
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#define TRX_CMD_TX_START 2
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#define TRX_CMD_FORCE_TRX_OFF 3
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#define TRX_CMD_FORCE_PLL_ON 4
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#define TRX_CMD_RX_ON 6
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#define TRX_CMD_TRX_OFF 8
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#define TRX_CMD_PLL_ON 9
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#define TRX_CMD_RX_AACK_ON 22
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#define TRX_CMD_TX_ARET_ON 25
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#define TRX_STATUS_P_ON 0
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#define TRX_STATUS_BUSY_RX 1
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#define TRX_STATUS_BUSY_TX 2
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#define TRX_STATUS_RX_ON 6
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#define TRX_STATUS_TRX_OFF 8
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#define TRX_STATUS_PLL_ON 9
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#define TRX_STATUS_SLEEP 15
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#define TRX_STATUS_BUSY_RX_AACK 17
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#define TRX_STATUS_BUSY_TX_ARET 18
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#define TRX_STATUS_RX_AACK_ON 22
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#define TRX_STATUS_TX_ARET_ON 25
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#define TRX_STATUS_RX_ON_NOCLK 28
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#define TRX_STATUS_RX_AACK_ON_NOCLK 29
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#define TRX_STATUS_BUSY_RX_AACK_NOCLK 30
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#define TRX_STATUS_STATE_TRANSITION 31
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#define TRX_STATUS_MASK 0x1f
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#define TRAC_STATUS_SUCCESS 0
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#define TRAC_STATUS_SUCCESS_DATA_PENDING 1
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#define TRAC_STATUS_SUCCESS_WAIT_FOR_ACK 2
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#define TRAC_STATUS_CHANNEL_ACCESS_FAILURE 3
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#define TRAC_STATUS_NO_ACK 5
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#define TRAC_STATUS_INVALID 7
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#endif // _AT86RF233_H_
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