145 lines
5.3 KiB
C
145 lines
5.3 KiB
C
/**
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* \file
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*
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* \brief HPL initialization related functionality implementation.
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*
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* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Subject to your compliance with these terms, you may use Microchip
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* software and any derivatives exclusively with Microchip products.
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* It is your responsibility to comply with third party license terms applicable
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* to your use of third party software (including open source software) that
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* may accompany Microchip software.
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*
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* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
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* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
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* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
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* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
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* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
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* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
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* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
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* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
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* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
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* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
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* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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*
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* \asf_license_stop
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*
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*/
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#include <hpl_gpio.h>
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#include <hpl_init.h>
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#include <hpl_gclk_base.h>
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#include <hpl_pm_config.h>
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#include <hpl_pm_base.h>
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#include <hpl_dma.h>
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#include <hpl_dmac_config.h>
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/* Referenced GCLKs (out of 0~7), should be initialized firstly
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* - GCLK 3 for DFLL48M
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*/
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#define _GCLK_INIT_1ST 0x00000008
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/* Not referenced GCLKs, initialized last */
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#define _GCLK_INIT_LAST 0x000000F7
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#define GCLK_CLKCTRL_ID_DFLL48M _U_(0)
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static void _init_clocks_hack()
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{
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NVMCTRL->CTRLB.bit.RWS = NVMCTRL_CTRLB_RWS_HALF_Val;
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PM->APBAMASK.bit.GCLK_ = true;
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GCLK->CTRL.bit.SWRST = true;
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while (GCLK->CTRL.bit.SWRST && GCLK->STATUS.bit.SYNCBUSY);
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SYSCTRL->OSC8M.bit.ONDEMAND = false;
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GCLK->GENDIV.reg =
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GCLK_GENDIV_ID(3) | // Select generator 3
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GCLK_GENDIV_DIV(64); // Set the division factor to 64
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// 4. Create generic clock generator 3 for the 15KHz signal of the DFLL
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GCLK->GENCTRL.reg =
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GCLK_GENCTRL_ID(3) | // Select generator 3
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GCLK_GENCTRL_SRC_OSC8M | // Select source OSC8M
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GCLK_GENCTRL_GENEN; // Enable this generic clock generator
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while (GCLK->STATUS.bit.SYNCBUSY) {}; // Wait for synchronization
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// 5. Configure DFLL with the
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GCLK->CLKCTRL.reg =
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GCLK_CLKCTRL_ID_DFLL48M | // Target is DFLL48M
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GCLK_CLKCTRL_GEN(3) | // Select generator 3 as source.
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GCLK_CLKCTRL_CLKEN; // Enable the DFLL48M
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while (GCLK->STATUS.bit.SYNCBUSY) {}; // Wait for synchronization
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// 6. Workaround to be able to configure the DFLL.
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SYSCTRL->DFLLCTRL.bit.ONDEMAND = false;
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while (!SYSCTRL->PCLKSR.bit.DFLLRDY) {}; // Wait for synchronization.
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// 7. Change the multiplication factor.
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SYSCTRL->DFLLMUL.bit.MUL = 3072; // 48MHz / (1MHz / 64)
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SYSCTRL->DFLLMUL.bit.CSTEP = 1; // Coarse step = 1
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SYSCTRL->DFLLMUL.bit.FSTEP = 1; // Fine step = 1
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while (!SYSCTRL->PCLKSR.bit.DFLLRDY) {}; // Wait for synchronization.
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// 8. Start closed-loop mode
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SYSCTRL->DFLLCTRL.reg |=
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SYSCTRL_DFLLCTRL_MODE | // 1 = Closed loop mode.
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SYSCTRL_DFLLCTRL_QLDIS; // 1 = Disable quick lock.
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while (!SYSCTRL->PCLKSR.bit.DFLLRDY) {}; // Wait for synchronization.
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// 9. Clear the lock flags.
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SYSCTRL->INTFLAG.bit.DFLLLCKC = 1;
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SYSCTRL->INTFLAG.bit.DFLLLCKF = 1;
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SYSCTRL->INTFLAG.bit.DFLLRDY = 1;
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// 10. Enable the DFLL
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SYSCTRL->DFLLCTRL.bit.ENABLE = true;
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while (!SYSCTRL->PCLKSR.bit.DFLLRDY) {}; // Wait for synchronization.
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// 11. Wait for the fine and coarse locks.
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while (!SYSCTRL->INTFLAG.bit.DFLLLCKC && !SYSCTRL->INTFLAG.bit.DFLLLCKF) {};
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// 12. Wait until the DFLL is ready.
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while (!SYSCTRL->INTFLAG.bit.DFLLRDY) {};
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// Switch the main clock speed.
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// 1. Set the divisor of generic clock 0 to 0
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GCLK->GENDIV.reg =
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GCLK_GENDIV_ID(0) | // Select generator 0
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GCLK_GENDIV_DIV(0);
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while (GCLK->STATUS.bit.SYNCBUSY) {}; // Wait for synchronization
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// 2. Switch generic clock 0 to the DFLL
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GCLK->GENCTRL.reg =
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GCLK_GENCTRL_ID(0) | // Select generator 0
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GCLK_GENCTRL_SRC_DFLL48M | // Select source DFLL
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GCLK_GENCTRL_IDC | // Set improved duty cycle 50/50
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GCLK_GENCTRL_GENEN; // Enable this generic clock generator
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while (GCLK->STATUS.bit.SYNCBUSY) {}; // Wait for synchronization
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}
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/**
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* \brief Initialize the hardware abstraction layer
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*/
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void _init_chip(void)
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{
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hri_nvmctrl_set_CTRLB_RWS_bf(NVMCTRL, CONF_NVM_WAIT_STATE);
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_pm_init();
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#if 0 // broken code from Atmel START. Please consider using an STM32 with CubeMX instead.
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_sysctrl_init_sources();
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#if _GCLK_INIT_1ST
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_gclk_init_generators_by_fref(_GCLK_INIT_1ST);
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#endif
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_sysctrl_init_referenced_generators();
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_gclk_init_generators_by_fref(_GCLK_INIT_LAST);
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#endif
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// actually functioning code from random SO thread:
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// https://electronics.stackexchange.com/questions/332569/how-to-configure-atmel-sam-d20-for-internal-48mhz-clock-source
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_init_clocks_hack();
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#if CONF_DMAC_ENABLE
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_pm_enable_bus_clock(PM_BUS_AHB, DMAC);
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_pm_enable_bus_clock(PM_BUS_APBB, DMAC);
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_dma_init();
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#endif
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}
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